In the fabrication of some power devices such as reverse-conductor insulated-gate bipolar transistors (RC-IGBTs), device structures are formed on both the front and back sides of a silicon wafer, which requires the process of double-sided patterning as well as alignment between patterns on the front and back sides of the silicon wafer.
The general practice for achieving the above device structures is one called back-side alignment, for which special lithographic apparatuses and processes are employed. Specifically, in a back-side alignment process, alignment marks are formed on the front side of a wafer, and are taken as alignment references during the back-side lithographic processes. As the silicon wafer is turned upside down when performing back-side alignment, i.e., its front side is facing downwards, a special method is needed to achieve the alignment. According to different light sources adopted, commonly used alignment methods are classified into those adopting infrared light and visible light. Moreover, according to different detecting modes, commonly used detecting methods are classified into reflection detecting and transmission detecting. Currently, all alignment methods adopted in practice are a combination of the above categories.
When infrared light is used, determined by its physical properties, both its reflectivity and transmissivity are affected by characteristics of the wafer and the process, for example, the wafer thickness, doping type and doping concentration of the wafer, and whether the pattern on the front side of the wafer is formed of metal. These will have great impacts on the intensity and signal to noise ratio (SNR) of infrared signals. Therefore, for a determined alignment mode, the process must be carried out in fixed steps, i.e., in which step the back-side lithography should be performed is strictly limited. Meanwhile, extremely high requirements are also imposed on the dopant type and concentration, which will severely limit the properties of the device. As a result, different apparatuses must be employed to produce specific devices with different properties, thus leading to a high production cost of the devices.
On the other hand, when visible light is used, as it cannot pass through a silicon wafer, one can only adopt the reflection type alignment. In such a mode, when performing the back-side lithographic process, the silicon wafer held by a wafer stage must be placed with the back side facing upwards, namely, with the front side where the alignment marks are formed facing downwards and contacting with the wafer stage, and thus holes must be drilled in the wafer stage in order to introduce light into the holes from the back side of the wafer stage. In order to avoid harming the wafer stage's function of holding the silicon wafer by suction, positions and sizes of such holes are limited, thus increasing the complexity of circuit layout design. Further, there are also strict requirements on a protective film that is coated on the front side of the wafer to protect the pattern formed thereon before the wafer is flipped over. For example, in order for visible light to pass through, such film must be transparent and have uniform and stable optical properties.
Overall, because all these methods require expensive special apparatuses and a corresponding specific process, the fabrication cost of this kind of devices has remained high.
Not limited to the above, other back-side processes such as back-side implantation and back-side metallization also require special apparatuses. Therefore, manufacturers have tried to avoid the use of such back-side processes if alternative solutions are available.
In addition, the breakdown voltage of certain types of devices is closely dependent on the thickness of the silicon wafer. Specifically, given the facts that the ratio of breakdown voltage to thickness for silicon is about 10V/μm, and that common consumer-level electronic products have an operating voltage range of 110 volts alternating current (VAC) to 380 VAC and a typical breakdown voltage of about 600 V, silicon substrates for silicon-based integrated devices are generally required to have a thickness of smaller than 100 μm, and typically, from 50 μm to 60 μm. Commonly employed silicon wafer fabrication processes cannot achieve a thickness smaller than 60 μm and must be aided by using carrier substrates, which are thin films commonly made of organic materials, glasses, silicon, metals and the like. Use of such carrier substrates greatly limits subsequent processes. For example, as carrier substrates made of organic materials or glasses cannot be sucked by electrostatic adsorption, when adopting such carrier substrates, all electrostatic adsorption apparatuses throughout the whole production line must be substituted with special suction apparatuses. Moreover, as metals and silicon are opaque materials, no back-side process is applicable when a carrier substrate formed of metal or silicon is applied.
Therefore, there is no effective double-sided patterning method suitable for mass production of thin silicon wafers (i.e., those with a thickness of smaller than 150 μm) at present.